The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely sophisticated devices that may be found in many different settings. Computer systems typically include a combination of hardware (e.g., semiconductors, circuit boards, etc.) and software (e.g., computer programs). As advances in semiconductor processing and computer architecture push the performance of the computer hardware higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
One component of a computer system that can have a dramatic impact on the performance of the computer system is the memory subsystem. Computer systems typically include one or more processors coupled to the memory subsystem via a processor bus. The memory subsystem typically includes a memory controller coupled to one or more Synchronous Dynamic Random Access Memory (SDRAM) modules via a memory data bus and associated control signals. The memory controller is responsible for accepting memory read and write (load and store) commands or requests from the processor, interfacing with the SDRAMs to perform a read or write command, and returning any data associated with the read operation from the SDRAMs back to the processor. The memory controller also has the task of managing memory bank timing, maximizing the utilization of the memory data bus, and optimizing memory accesses, such as prioritizing reads over writes when possible.
Optimizing memory accesses has been a fundamental issue with increasing computer system performance. One memory access issue that memory controllers have struggled with is the selection of read commands versus write commands. Typically, read commands are the limiting factor for system performance because either the processor must wait for the read data, in order to continue to execute instructions, or the processor prefetches read data and then attempts to hide memory latency. Write commands typically are not as serious an issue since the processor considers them to be complete as soon as the processor sends the write data to the memory controller. Memory controllers, however, have a fixed number of buffers (or queues) to hold write commands and data. Once the buffers are nearly full, the memory controller needs to signal the processor that no new commands can be taken, which stalls the bus, due to possibly overflowing the write queue in the memory controller. This stalling can cause extra delay for all processor commands; thus, write commands can become a performance issue for the read commands.
Thus, a better way is needed to choose the appropriate time to send write commands to the memory, in order to allow to increase performance.